1. Field of the Invention
Embodiments of the present invention relate to a method of fabricating a semiconductor package, and a semiconductor package formed thereby.
2. Description of the Related Art
As the size of electronic devices continue to decrease, the associated semiconductor packages that operate them are being designed with smaller form factors, lower power requirements and higher functionality. Currently, sub-micron features in semiconductor fabrication are placing higher demands on package technology including higher lead counts, reduced lead pitch, minimum footprint area and significant overall volume reduction.
One branch of semiconductor packaging involves the use of a leadframe, which is a thin layer of metal on which one or more semiconductor die are mounted. The leadframe includes electrical leads for communicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices. Common leadframe-based packages include plastic small outlined packages (PSOP), thin small outlined packages (TSOP), shrink small outline packages (SSOP) and thin quad flat packages (TQFP). These packages include leads which extend out from the sides of the encapsulated package, which leads may be surface mounted to a host device such as a printed circuit board (PCB) as by soldering. Another common type of leadframe-based package is a leadless package. These include dual flat no-lead (DFN) and quad flat no-lead (QFN) packages. These packages do not have leads extending out of the sides of the package, but instead have exposed terminals at a bottom surface of the package for soldering to a host device such as a PCB.
FIG. 1 shows a leadframe 20 of a QFN package 22 during fabrication. While a single leadframe 20 is shown, the leadframe package 22 would typically be fabricated on a strip of leadframes to achieve economies of scale. A typical QFN leadframe 20 may include fourteen contact terminals 24 per side, though there may be more or less terminals in alternative configurations. As seen in prior art FIG. 2, the terminals 24 are exposed at the bottom surface of the leadframe. The leadframe 20 may further include a die attach pad 26 for structurally supporting one or more semiconductor die 30 on leadframe 20. While die attach pad 26 may provide a path to ground, it conventionally does not carry signals to or from the semiconductor die 30. In certain leadframe configurations, it is known to omit die attach pad 26 and instead attach the semiconductor die directly to the leadframe leads in a so-called chip on lead (COL) configuration.
In embodiments including a die paddle, the die paddle may be affixed to the leadframe strip (not shown) via tie bars 28 extending from all four corners of the die paddle 26. The tie bars 28 support the die paddle on the leadframe strip prior to singulation, and also serve as a path to ground.
The one or more semiconductor die 30 may include one or more flash memory die and/or a controller die. The semiconductor die 30 may include die bond pads 32 on a top surface. Once the semiconductor die 30 is mounted to the leadframe 20, a wire bond process is performed whereby bond pads are electrically coupled to respective electrical terminals 24 using a delicate wire 36 (one of which being labeled in FIG. 1). The assignment of a bond pad 32 to a particular electrical terminal 24 is defined by industry standard specification.
After the one or more die 30 are mounted and electrically coupled to the leadframe, the die 30 and a portion of the leadframe 20 may be encapsulated in a mold compound 40 as seen in the side view of prior art FIG. 3 to complete the leadframe package 20 fabrication. Thereafter, the terminals 24 exposed at the bottom surface of the leadframe package 22 may be soldered to a printed circuit board in a surface mount process to electrically couple the package 22 to the printed circuit board.
Where die 30 is for example a controller die, it is known to provide bond pads 32 around multiple edges on the top surface owing to the large number of electrical connections required between the die 30 and leadframe 20. Die 30 may include many more bond pads 32 than are shown in the Figures, and it is difficult to find room on the leadframe to bond out each of the required electrical connections to terminals 24.
Moreover, certain terminals 24 that are spaced apart from each other need to be electrically connected to each other. Conventionally, this is done by circuitry on the printed circuit board to which the leadframe package 22 is affixed.